A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/s...

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Bibliographic Details
Published inDigest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 pp. 128 - 129
Main Authors Ranica, R., Villaret, A., Malinge, P., Mazoyer, P., Lenoble, D., Candelier, P., Jacquet, F., Masson, P., Bouchakour, R., Fournel, R., Schoellkopf, J.P., Skotnicki, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2004
Subjects
CMOS process
Dynamic programming
Energy consumption
Impact ionization
Logic devices
MOSFET circuits
Performance evaluation
Silicon
Voltage
Writing
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Summary:A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.
ISBN:0780382897
9780780382893
DOI:10.1109/VLSIT.2004.1345433