A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals

• Published in: ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) pp. 53 - 56
• Main Authors: Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Clocks; Costs; Engines; Fabrication; Filtering; Graphics; Large scale integration; Random access memory; Rendering (computer graphics); Table lookup
• ISBN: 0780379950; 9780780379954
• DOI: 10.1109/ESSCIRC.2003.1257070

A low-power 3D rendering engine with 2 texture units and 29Mb embedded DRAM is designed and integrated into an LSI for portable 3G multimedia terminals. Texture-mapped 3D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of clock gating, precision-controlled look-up table dividers, texture address alignment and embedded DRAM. The performance is scalable and it reaches up to 100Mpixels/s and 400 Mtexles/s at 50MHz. The chip is implemented with 0.16/spl mu/m pure DRAM process to reduce the fabrication cost. The logic and DRAM consume 46mm/sup 2/ and 140mW at 33MHz operation. The 3D graphics images are successfully demonstrated by the fabricated chip on the PDA system board.