A folded-channel MOSFET for deep-sub-tenth micron era

Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process....

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Bibliographic Details
Published inInternational Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) pp. 1032 - 1034
Main Authors Hisamoto, D., Wen-Chin Lee, Kedzierski, J., Anderson, E., Takeuchi, H., Asano, K., Tsu-Jae King, Bokor, J., Chenming Hu
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Dielectric materials
Electron devices
Etching
Fabrication
Immune system
Laboratories
Lithography
MOSFET circuits
Silicon germanium
Steel
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Summary:Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process. The special features of the structure are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short.
ISBN:0780347749
9780780347748
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.1998.746531