Computing optimal clock schedules

The author considers the problem of optimizing the parameters of a multiphase clock for a circuit containing both edge-triggered flip-flops and level-sensitive latches. He demonstrates that recently proposed linear programming (LP) approaches to this problem require excessive computation time. An al...

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Bibliographic Details
Published in[1992] Proceedings 29th ACM/IEEE Design Automation Conference pp. 399 - 404
Main Author Szymanski, T.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1992
Subjects
Clocks
Combinational circuits
Delay
Flip-flops
Integrated circuit interconnections
Latches
Linear programming
Multidimensional systems
Processor scheduling
Timing
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ISBN9780818628221
0818628227
ISSN0738-100X
DOI10.1109/DAC.1992.227771

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Summary:The author considers the problem of optimizing the parameters of a multiphase clock for a circuit containing both edge-triggered flip-flops and level-sensitive latches. He demonstrates that recently proposed linear programming (LP) approaches to this problem require excessive computation time. An alternative method is proposed in which LP constraints are generated selectively, thus allowing fast solution. Various formulations of short path constraints are discussed, as are experimental results for large circuits.< >
ISBN:9780818628221
0818628227
ISSN:0738-100X
DOI:10.1109/DAC.1992.227771