Synthesis of sequential circuits with clock control to improve testability

We propose a new synthesis technique for finite state machines that improves their testability by disabling the clock to a subset of the flip-flops. Distance-matrix results with and without the clock control demonstrate dramatic improvement in the average and worst-case distances between pairs of st...

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Bibliographic Details
Published inProceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) pp. 472 - 477
Main Authors Einspahr, K.L., Mehta, S.K., Seth, S.C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Circuit synthesis
Circuit testing
Clocks
Computer science
Controllability
Encoding
Logic
Navigation
Sequential analysis
Sequential circuits
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Summary:We propose a new synthesis technique for finite state machines that improves their testability by disabling the clock to a subset of the flip-flops. Distance-matrix results with and without the clock control demonstrate dramatic improvement in the average and worst-case distances between pairs of states. The experimental results using available sequential ATPG tools further verify that the scheme allows significantly shorter tests to be generated with comparable fault coverage.
ISBN:9780818682773
0818682779
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.1998.741659