Simultaneous cycle-time reduction and output enhancement in a fully loaded foundry wafer fab
A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output in...
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Published in | Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) pp. 63 - 66 |
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Main Authors | , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
2000
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Subjects | |
Online Access | Get full text |
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Summary: | A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output increase of over 20%. In the mean time, the fab WIP level was reduced by more than 20% without any compromise in line-yield or customer delivery. |
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ISBN: | 9780780373921 0780373928 |
ISSN: | 1523-553X |
DOI: | 10.1109/ISSM.2000.993617 |