Simultaneous cycle-time reduction and output enhancement in a fully loaded foundry wafer fab

A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output in...

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Bibliographic Details
Published inProceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) pp. 63 - 66
Main Authors Ho, C.M., Chen, T.C., Hseih, P., Chu, C., Houn, E., Su, K.J., Wang, P.M., Yew, W.C., Sun, S.W.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Capacity planning
EPROM
Foundries
Lithography
Microelectronics
Monitoring
Production control
Sun
Technological innovation
Throughput
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Summary:A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output increase of over 20%. In the mean time, the fab WIP level was reduced by more than 20% without any compromise in line-yield or customer delivery.
ISBN:9780780373921
0780373928
ISSN:1523-553X
DOI:10.1109/ISSM.2000.993617