Distributed design-space exploration for high-level synthesis systems

A parallel algorithm for design-space exploration and trade-off analysis is presented. Coarse-grained parallelism is introduced by generating multiple module bags and performing scheduling and performance analysis of the data flow graph for each module bag in parallel. This algorithm was implemented...

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Bibliographic Details
Published in[1992] Proceedings 29th ACM/IEEE Design Automation Conference pp. 644 - 650
Main Authors Dutta, R., Roy, J., Vemuri, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1992
Subjects
Algorithm design and analysis
Clocks
Cost function
Flow graphs
High level synthesis
Libraries
Monitoring
Parallel processing
Processor scheduling
Scheduling algorithm
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ISBN9780818628221
0818628227
ISSN0738-100X
DOI10.1109/DAC.1992.227806

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Summary:A parallel algorithm for design-space exploration and trade-off analysis is presented. Coarse-grained parallelism is introduced by generating multiple module bags and performing scheduling and performance analysis of the data flow graph for each module bag in parallel. This algorithm was implemented on a multiple processor machine as part of a distributed high-level synthesis system. Experimental results showed reduction in search time, improvement in design quality, and close-to-linear speedup.< >
ISBN:9780818628221
0818628227
ISSN:0738-100X
DOI:10.1109/DAC.1992.227806