At-speed delay testing of synchronous sequential circuits

Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test...

Full description

Saved in:
Bibliographic Details
Published in[1992] Proceedings 29th ACM/IEEE Design Automation Conference pp. 177 - 181
Main Authors Pomeranz, I., Reddy, S.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1992
Subjects
Circuit faults
Circuit testing
Clocks
Combinational circuits
Delay effects
Flip-flops
Robustness
Sequential analysis
Sequential circuits
System testing
Online AccessGet full text
ISBN9780818628221
0818628227
ISSN0738-100X
DOI10.1109/DAC.1992.227840

Cover

Abstract Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length.< >
AbstractList Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length.< >
Author Reddy, S.M.
Pomeranz, I.
Author_xml – sequence: 1
  givenname: I.
  surname: Pomeranz
  fullname: Pomeranz, I.
  organization: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
– sequence: 2
  givenname: S.M.
  surname: Reddy
  fullname: Reddy, S.M.
  organization: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
BookMark eNotj81KxDAURgOO4Dh2LbjKC7Tm5qe5WZaqozDgRsHdkGlvNVLbsUkXfXsHxm9zFgcOfNdsNYwDMXYLogAQ7v6hqgtwThZSWtTigmXOokDAUqKUsGJrYRXmIMTHFcti_BanGYNSqDVzVcrjkajlLfV-4YliCsMnHzsel6H5msZhnCOP9DvTkILveROmZg4p3rDLzveRsn9u2PvT41v9nO9ety91tcsDWJlyg0I2vtFaHjxIWwI5I4z21tmOpOjcAbDF0pRWgyKlEE--M6haQwSk1YbdnbuBiPbHKfz4admfv6o_M9FIBw
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/DAC.1992.227840
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore Digital Library
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EndPage 181
ExternalDocumentID 227840
GroupedDBID 123
29O
6IE
6IF
6IH
6IK
6IL
6IM
6IN
AAJGR
AAWTH
ACGFS
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
IJVOP
IPLJI
M43
OCL
RIE
RIL
RNS
ID FETCH-LOGICAL-i172t-5802cac442ba12761e95054a797fe20f9b18d86567413e3388950f583d5ee1e43
IEDL.DBID RIE
ISBN 9780818628221
0818628227
ISSN 0738-100X
IngestDate Tue Aug 26 16:39:36 EDT 2025
IsPeerReviewed false
IsScholarly true
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i172t-5802cac442ba12761e95054a797fe20f9b18d86567413e3388950f583d5ee1e43
PageCount 5
ParticipantIDs ieee_primary_227840
PublicationCentury 1900
PublicationDate 19920000
PublicationDateYYYYMMDD 1992-01-01
PublicationDate_xml – year: 1992
  text: 19920000
PublicationDecade 1990
PublicationTitle [1992] Proceedings 29th ACM/IEEE Design Automation Conference
PublicationTitleAbbrev DAC
PublicationYear 1992
Publisher IEEE Comput. Soc. Press
Publisher_xml – name: IEEE Comput. Soc. Press
SSID ssj0000558203
ssj0004161
Score 1.3875629
Snippet Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing...
SourceID ieee
SourceType Publisher
StartPage 177
SubjectTerms Circuit faults
Circuit testing
Clocks
Combinational circuits
Delay effects
Flip-flops
Robustness
Sequential analysis
Sequential circuits
System testing
Title At-speed delay testing of synchronous sequential circuits
URI https://ieeexplore.ieee.org/document/227840
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjZ07T8MwEMct6AQLUIp4ywNr0thxEmesClWFBGKgUrcqcc6oAiUVSYby6TnbaXmIgc15SJHtU-7Ovv_PhNykoUZDKUJP8iTwRJZwL8t0YGxZhxiRswRMovjwGE9n4n4ezTvOttXCAIAtPgPfNO1eflGp1iyVDY1sU2B-votW5qRa2-WUIIqk3VDcSCKZRaWiARt6aTC36EeG4Ts6xKQD72yuWYf8YUE6vB2NjYCP--5bP85csS5ncuC03LUlFZpKk1e_bXJfffziOP6zN4dk8KXto09br3VEdqDsk_1vWMJjko4ar17hC9QgJNe0MSSO8oVWmtbrUhmcbtXW1FVh4x_ijarlu2qXTT0gs8nd83jqdUcseEuMXBovkgFXmRKC5xnjScwgxZAIpyxNNPBApzmThcSYDwOPEDCdlfhcRzi7EQADEZ6QXlmVcEqoSriUMaRxITDdVjLDVKVAC9FhFGI7OyN9MwaLlaNoLFz3z_-8e0H2XFmsWeq4JL3mvYUrdP5Nfm2n_RP_wqXW
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjZ07T8MwEMctVAZgAUoRbzywJo0dO3HGqlAVaCuGVupWpY6NKlBSNclQPj1nJy0PMbA5Dymyfcrd2ff_GaG7yNdgKInvCBp6DotD6sSx9owtax8ichIqkygOR0F_wp6mfFpztq0WRilli8-Ua5p2Lz_JZGmWytpGtskgP98Ft894JdbaLqh4nAu7pbgRRRILSwUTNvxSb2rhjwQCeHCJYY3e2VyTGvpDvKh93-kaCR91q6_9OHXFOp3eYaXmzi2r0NSavLllMXflxy-S4z_7c4RaX-o-_LL1W8doR6VNdPANTHiCok7h5Et4ARuI5BoXhsWRvuJM43ydSgPUzcocV3XY8I94x3KxkuWiyFto0nsYd_tOfciCs4DYpXC48KiMJWN0HhMaBkRFEBTBpEWhVtTT0ZyIREDUB6GHryChFfBcc5hfrhRRzD9FjTRL1RnCMqRCBCoKEgYJtxQxJCsJ2Ij2uQ_t-Bw1zRjMlhVHY1Z1_-LPu7dorz8eDmaDx9HzJdqvimTNwscVahSrUl1DKFDMb6wJfALoG6kj
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=%5B1992%5D+Proceedings+29th+ACM%2FIEEE+Design+Automation+Conference&rft.atitle=At-speed+delay+testing+of+synchronous+sequential+circuits&rft.au=Pomeranz%2C+I.&rft.au=Reddy%2C+S.M.&rft.date=1992-01-01&rft.pub=IEEE+Comput.+Soc.+Press&rft.isbn=9780818628221&rft.issn=0738-100X&rft.spage=177&rft.epage=181&rft_id=info:doi/10.1109%2FDAC.1992.227840&rft.externalDocID=227840
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0738-100X&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0738-100X&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0738-100X&client=summon