At-speed delay testing of synchronous sequential circuits

Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test...

Full description

Saved in:
Bibliographic Details
Published in[1992] Proceedings 29th ACM/IEEE Design Automation Conference pp. 177 - 181
Main Authors Pomeranz, I., Reddy, S.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1992
Subjects
Circuit faults
Circuit testing
Clocks
Combinational circuits
Delay effects
Flip-flops
Robustness
Sequential analysis
Sequential circuits
System testing
Online AccessGet full text
ISBN9780818628221
0818628227
ISSN0738-100X
DOI10.1109/DAC.1992.227840

Cover

More Information
Summary:Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length.< >
ISBN:9780818628221
0818628227
ISSN:0738-100X
DOI:10.1109/DAC.1992.227840