Some limitations to speed-independence in asynchronous circuits

Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamen...

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Bibliographic Details
Published inProceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems pp. 104 - 111
Main Authors Bush, M.E., Josephs, M.B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Asynchronous circuits
Circuit synthesis
Delay
Interference
Logic circuits
Logic design
Logic gates
Pulse circuits
Very large scale integration
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Summary:Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory.
ISBN:9780818672989
0818672986
DOI:10.1109/ASYNC.1996.494442