The design of a systolic architecture to implement graphic transformations

A new systolic graphic array architecture is proposed in order to achieve the high computational throughput necessary to generate real-time processing. The proposed systolic architecture implements graphic transformations such as translations, scaling, and rotations on three dimensional vertices. Th...

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Bibliographic Details
Published in[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications pp. 170 - 175
Main Authors Papadourakis, G.M., Bebis, G.N.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1991
Subjects
Computational modeling
Computer architecture
Computer graphics
Computer science
Displays
Image generation
Signal processing algorithms
Systolic arrays
Throughput
Very large scale integration
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Summary:A new systolic graphic array architecture is proposed in order to achieve the high computational throughput necessary to generate real-time processing. The proposed systolic architecture implements graphic transformations such as translations, scaling, and rotations on three dimensional vertices. The logarithmic number system is utilized to further increase the computational throughput. A comparison between the proposed systolic architecture and the Weitek 7100 SME graphic processor in terms of speed is performed.< >
ISBN:9780818621413
0818621419
DOI:10.1109/CMPEUR.1991.257376