Top-down design using cycle based simulation: an MPEG A/V decoder example

This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 audio/video decoder design example illustrates the use of this top-down approach. Most of...

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Bibliographic Details
Published inProceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222) pp. 400 - 405
Main Authors Hocevar, D.E., Ching-Yu Hung, Pickens, D., Sriram, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Decoding
Emulation
Very large scale integration
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Summary:This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 audio/video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well.
ISBN:0818684097
9780818684098
ISSN:1066-1395
DOI:10.1109/GLSV.1998.665333