ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters

In this work, implementation trade-offs for ASICimplementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is a...

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Bibliographic Details
Published in2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
Main Authors Khan, Mohd. Tasleem, Gustafsson, Oscar
Format Conference Proceeding
LanguageEnglish
Published IEEE 07.08.2022
Subjects
Adaptive filters
Circuits and systems
Energy consumption
Logic gates
Parallel processing
Timing
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Summary:In this work, implementation trade-offs for ASICimplementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE.
ISSN:1558-3899
DOI:10.1109/MWSCAS54063.2022.9859296