A 14b 200MHz power-efficient pipelined flash-SAR ADC

This paper presents a 14-bit 200MHz power-efficient pipelined flash-SAR ADC. A 5-bit front-end without a dedicated sample-and-hold amplifier (SHA) is adopted in the first stage. A 10-bit flash-SAR ADC which is composed of a 3.5-bit flash ADC and a 7-bit asynchronous SAR ADC is used as the second sta...

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Bibliographic Details
Published in2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) pp. 1 - 3
Main Authors Jifang Wu, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2014
Subjects
Abstracts
CMOS integrated circuits
CMOS technology
Frequency conversion
Logic gates
Switching circuits
Timing
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Summary:This paper presents a 14-bit 200MHz power-efficient pipelined flash-SAR ADC. A 5-bit front-end without a dedicated sample-and-hold amplifier (SHA) is adopted in the first stage. A 10-bit flash-SAR ADC which is composed of a 3.5-bit flash ADC and a 7-bit asynchronous SAR ADC is used as the second stage. To achieve high performance with high power-efficiency in the proposed ADC, correlated level-shifting (CLS), range-scaling and capacitor sharing techniques are employed. The ADC is designed using a 65nm CMOS technology. Transient simulations with noise demonstrate that the ADC achieves a SNDR of 75.86 dB and a SFDR of 87.1 dB with an input frequency of 93.19MHz. The ADC core consumes 11.4 mW at a 1.2V supply voltage.
ISBN:9781479932962
1479932965
DOI:10.1109/ICSICT.2014.7021241