Statistical aspects of FinFET based SRAM metrics subject to process and statistical variability

Variability in nanoscale FinFETs brings huge challenges to SRAM design. Using recently developed unified variability compact models, in this paper we investigate the impact of long-range process variation and local statistical variability on various 6T-SRAM metrics including static noise margin, bit...

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Bibliographic Details
Published in2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) pp. 1 - 3
Main Authors Xingsheng Wang, Binjie Cheng, Millar, Campbell, Reid, Dave, Asenov, Asen
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2014
Subjects
FinFETs
Integrated circuit modeling
Layout
Measurement
Random access memory
Semiconductor process modeling
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ISBN9781479932962
1479932965
DOI10.1109/ICSICT.2014.7021284

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Summary:Variability in nanoscale FinFETs brings huge challenges to SRAM design. Using recently developed unified variability compact models, in this paper we investigate the impact of long-range process variation and local statistical variability on various 6T-SRAM metrics including static noise margin, bitline write margin and retention leakage in two types of cell layout. The results show that these metrics are affected by different types of variability with different sensitivities.
ISBN:9781479932962
1479932965
DOI:10.1109/ICSICT.2014.7021284