Effects of soldering voids on junction to case thermal resistance in applying electrical testing method

• Published in: 2014 10th International Conference on Reliability, Maintainability and Safety (ICRMS) pp. 772 - 776
• Main Authors: Jincheng You, Bin Zhou, Ruguan Li, Guoyuan Li
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2014
• Subjects: Electrical resistance measurement; electrical testing method; Electronic packaging thermal management; Finite element analysis; junction to case thermal resistance; Junctions; Temperature measurement; Thermal resistance; voids
• DOI: 10.1109/ICRMS.2014.7107303

Void in solder layer is one of the important factors resulting in semiconductor chip failure due to poor heat dissipation, so the quality of solder layer is essential for heat distribution and reliability in electronic devices. This article is aimed at analyzing the impact of solder layer voids area on junction to case thermal resistance of devices in applying electrical testing method. The thermal resistance was measured by T3Ster (the Thermal Transient Tester) which adopts thermal transient testing technique. To verify the results, this study employed infrared microscope test the samples under the same conditions, and then used FEM (the finite element method) to simulate the relationships between the thermal resistance and voids in solder joint. Results show that the junction to case thermal resistance of the device increases with the increase in solder layer void percentage but without obvious linear relationship. For the same type devices with fine uniformity, the difference of R th (j-c) is mainly caused by diversity in solder layer void area. Conclusions mentioned above can be used to guide the design of derating for military devices.