Challenges for InGaAs n-MOSFETs in the future generation sub-10nm CMOS logic devices

• Published in: 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) pp. 1 - 4
• Main Authors: Ming-Fu Li, Shenwei Li, Daming Huang, Ye, Peide D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2014
• Subjects: Abstracts; Gallium arsenide; High K dielectric materials; Logic gates; MOSFET circuits; Stress
• ISBN: 9781479932962; 1479932965
• DOI: 10.1109/ICSICT.2014.7021326

(1). The performance of n-MOSFETs in ultimate scaling limit (gate length approaches ballistic limit, gate oxide approaches quantum capacitance limit ) is assessed. Thick body (t body >10nm) InGaAs channel with isotropic Γ conduction valley is not a good choice. The small conduction mass m C * over-compensated by small density of states mass m D *, leading to small drain current I d . Ultrathin body t body <;4nm InGaAs with [110] surface orientation can induce the lowest very anisotropic L valleys with large m D *. When choosing the suitable channel direction with small m C *, the FET may boost I dsat to 15mA/μm at V g -V th =0.4V, increased by a factor of 6 comparing to the thick body with Γ valley conduction, and a factor of 30 comparing to the so far best record of I dsat = 0.5mA/μm at 0.5V bias for the real InGaAs n-MOSFET. A FinFET structure on [100] InGaAs substrate with [110] Fin wall surface and <;4nm Fin width is proposed to implement the L valley conduction with largest I dsat .