Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices

• Published in: 2007 IEEE Custom Integrated Circuits Conference pp. 615 - 618
• Main Authors: Devoivre, T., Rouse, R., Verghese, N., Hurat, P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2007
• Subjects: Analytical models; Circuit simulation; Current density; Geometry; Predictive models; Semiconductor process modeling; Shape measurement; Silicon; Solid modeling; Stress
• ISBN: 9781424407866; 1424407869
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2007.4405807

A current density-based model that incorporates narrow width effects is proposed to predict the drawn current of transistors that exhibit non-uniform device geometry. A continuous, integrable, analytical model of current density that includes the details of stress, edge effects and dopant loss/pileup is first calibrated to silicon data or existing SPICE models. Using the active and poly contours of the actual transistor shape obtained from a lithography-like simulation with an enriched model or directly from SEM images, the current density model is integrated over the width of the transistor to obtain its drawn current. From this predicted current, equivalent transistor parameters for circuit simulation can be extracted. Comparison to silicon drive current measurements of poly T and active T structures on a ST 65 nm process show excellent correlation, with an average difference of less than 0.5% for active shapes and 0.8% for poly shapes.