Semi-Supervised Learning and ASIC Path Verification

To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statist...

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Bibliographic Details
Published in2018 First International Conference on Artificial Intelligence for Industries (AI4I) pp. 1 - 4
Main Authors Obert, James, Mannos, Tom J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2018
Subjects
ASIC Design Assurance
ASIC Integrity
ASIC Verification
Capacitance
Delays
Mathematical model
Pins
Registers
Semisupervised learning
Supply Chain Integrity
Trusted ASIC Design
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Summary:To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) formats are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-supervised learning techniques are powerful tools in characterizing variations within STA path data and has much potential for identifying anomalies in ASIC RTL and GDSII design data.
DOI:10.1109/AI4I.2018.8665713