A 1.6-2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOS

• Published in: 2011 Proceedings of the ESSCIRC (ESSCIRC) pp. 299 - 302
• Main Authors: Lindstrand, J., Bryant, C., Tormanen, M., Sjoland, H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2011
• Subjects: CMOS; CMOS integrated circuits; CMOS technology; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik; Engineering and Technology; Hybrid EER; Injection lock; Logic gates; Power amplifier; Power amplifiers; Power efficiency; Power generation; Poweramplifier; Teknik; Transistors; Wideband
• ISBN: 9781457707032; 1457707039
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIRC.2011.6044966

This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52×0.48mm 2 including pads.