Backside chip effect on latent relaxation in irradiated MOS devices
Latent interface trap build-up in MOS transistors is found to be governed by H/sub 2/ diffusion through the silicon substrate. The main source of H/sub 2/ is probably located on the back interface of the silicon wafer.
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Published in | 2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Vol. 1; pp. 379 - 382 vol.1 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
2000
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Abstract | Latent interface trap build-up in MOS transistors is found to be governed by H/sub 2/ diffusion through the silicon substrate. The main source of H/sub 2/ is probably located on the back interface of the silicon wafer. |
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AbstractList | Latent interface trap build-up in MOS transistors is found to be governed by H/sub 2/ diffusion through the silicon substrate. The main source of H/sub 2/ is probably located on the back interface of the silicon wafer. |
Author | Pershenkov, V.S. Meshurov, O.V. Emelianov, V.V. Cherepko, S.V. |
Author_xml | – sequence: 1 givenname: V.V. surname: Emelianov fullname: Emelianov, V.V. organization: Res. Inst. of Sci. Instrum., Moscow, Russia – sequence: 2 givenname: O.V. surname: Meshurov fullname: Meshurov, O.V. – sequence: 3 givenname: V.S. surname: Pershenkov fullname: Pershenkov, V.S. – sequence: 4 givenname: S.V. surname: Cherepko fullname: Cherepko, S.V. |
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Snippet | Latent interface trap build-up in MOS transistors is found to be governed by H/sub 2/ diffusion through the silicon substrate. The main source of H/sub 2/ is... |
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StartPage | 379 |
SubjectTerms | Annealing Delay effects Electron traps Hydrogen MOS devices MOSFETs Packaging Silicon Temperature Threshold voltage |
Title | Backside chip effect on latent relaxation in irradiated MOS devices |
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