Backside chip effect on latent relaxation in irradiated MOS devices

Latent interface trap build-up in MOS transistors is found to be governed by H/sub 2/ diffusion through the silicon substrate. The main source of H/sub 2/ is probably located on the back interface of the silicon wafer.

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Bibliographic Details
Published in2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Vol. 1; pp. 379 - 382 vol.1
Main Authors Emelianov, V.V., Meshurov, O.V., Pershenkov, V.S., Cherepko, S.V.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Annealing
Delay effects
Electron traps
Hydrogen
MOS devices
MOSFETs
Packaging
Silicon
Temperature
Threshold voltage
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Summary:Latent interface trap build-up in MOS transistors is found to be governed by H/sub 2/ diffusion through the silicon substrate. The main source of H/sub 2/ is probably located on the back interface of the silicon wafer.
ISBN:0780352351
9780780352353
DOI:10.1109/ICMEL.2000.840594