Standard CMOS voltage multipliers architectures for UHF RFID applications : study and implementation

An analysis of RFID multipliers architectures is presented. An analytic model of classical Mosfet multiplier is given, which permits to determine the main design parameters of this kind of circuit and their impacts on efficiency. Thanks to this study a new architecture is proposed in order to increa...

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Bibliographic Details
Published in2007 IEEE International Conference on RFID pp. 115 - 120
Main Authors Bergeret, E., Gaubert, J., Pannier, P.
Format Conference Proceeding
LanguageEnglish
Japanese
Published 2007
Subjects
CMOS process
Costs
Impedance
Radio frequency
Radiofrequency identification
Receiving antennas
Schottky diodes
Transmitting antennas
USA Councils
Voltage
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Summary:An analysis of RFID multipliers architectures is presented. An analytic model of classical Mosfet multiplier is given, which permits to determine the main design parameters of this kind of circuit and their impacts on efficiency. Thanks to this study a new architecture is proposed in order to increase efficiency. The two multipliers are designed and implemented in the same standard 0.18 mu m CMOS process. Measurements have been done and show functionality of the multipliers and improvement between the architectures.
ISBN:1424410126
9781424410125
ISSN:2374-0221
2573-7635
DOI:10.1109/RFID.2007.346158