Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design

• Published in: 2008 Design, Automation and Test in Europe pp. 1250 - 1255
• Main Authors: Verma, A.K., Brisk, P., Ienne, P.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.03.2008
• Subjects: Added delay; Adders; Circuit analysis; Circuit synthesis; Cryptography; Digital arithmetic; Error correction; Frequency; Natural languages; Performance analysis
• ISBN: 3981080130; 9783981080131
• ISSN: 1530-1591; 1558-1101
• DOI: 10.1109/DATE.2008.4484850

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, and circuits with performance close to these bounds have been designed. In this paper, we present a novel adder design that is exponentially faster than traditional adders; however, it produces incorrect results, deterministically, for a very small fraction of input combinations. We have also constructed a reliable version of this adder that can detect and correct mistakes when they occur. This creates the possibility of a variable-latency adder that produces a correct result very fast with extremely high probability; however, in some rare cases when an error is detected, the correction term must be applied and the correct result is produced after some time. Since errors occur with extremely low probability, this new type of adder is significantly faster than state-of-the-art adders when the overall latency is averaged over many additions.