A hierarchical formal approach to verifying side-channel resistant cryptographic processors

This paper presents a hierarchical formal verification method for cryptographic processors based on a combination of a word-level computer algebra procedure and a bit-level decision procedure using PPRM (Positive Polarity Reed-Muller) expansion. In the proposed method, the entire datapath structure...

Full description

Saved in:
Bibliographic Details
Published in2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) pp. 76 - 79
Main Authors Okamoto, Kotaro, Homma, Naofumi, Aoki, Takafumi, Morioka, Sumio
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2014
Subjects
Algebra
arithmetic circuits
Computers
cryptographic processors
Cryptography
design methodology for secure hardware
formal design
Galois fields
Polynomials
Program processors
Resistance
Online AccessGet full text

Cover

More Information
Summary:This paper presents a hierarchical formal verification method for cryptographic processors based on a combination of a word-level computer algebra procedure and a bit-level decision procedure using PPRM (Positive Polarity Reed-Muller) expansion. In the proposed method, the entire datapath structure of a cryptographic processor is described in the form of a hierarchical graph . The correctness of the entire circuit function is verified on this graph representation, by the algebraic method, and the function of each component is verified by the PPRM method, respectively. We have applied the proposed verification method to a complicated AES (Advanced Encryption Standard) circuit with a masking countermeasure against side-channel attack. The results show that the proposed method can verify such practical circuit automatically within 4 minutes while the conventional methods fail.
DOI:10.1109/HST.2014.6855572