Computing architecture to perform approximated simulated annealing for Ising models

• Published in: 2016 IEEE International Conference on Rebooting Computing (ICRC) pp. 1 - 8
• Main Authors: Okuyama, Takuya, Yoshimura, Chihiro, Hayashi, Masato, Yamaoka, Masanao
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.10.2016
• Subjects: Annealing; Computer architecture
• DOI: 10.1109/ICRC.2016.7738673

In the near future, the techniques to solve combinatorial optimization problems will become important in various fields and require large computing power. However, the performance growth of von Neumann architecture will slow down due to the end of semiconductor scaling. To resolve this problem, a computing architecture is proposed that maps the optimization problems to the ground state search of Ising models. The authors implemented the architecture, which finds the ground state by circuit operations inspired by SA, in CMOS circuits. The architecture adopts a modified algorithm using a majority function to simplify circuits. Though the power efficiency can be estimated to be 1800 times higher than that of a CPU, the modification deteriorates solution quality because it breaks the detailed balance condition. This paper presents a computing architecture that performs SA for Ising models approximately. The architecture satisfies the condition by utilizing the fact that the output of the majority voter circuit with stochastically processed inputs approximately behaves in accordance with the Glauber dynamics. Simulations demonstrate that solution quality of the proposed architecture is as good as that of SA. Our architecture can be power-efficient because the rate of increase in the number of transistors is less than 42%.