Bit Cost Scalable (BiCS) flash technology for future ultra high density storage devices

We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it to Pipe-shaped BiCS flash me...

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Bibliographic Details
Published inProceedings of 2010 International Symposium on VLSI Technology, System and Application pp. 130 - 131
Main Authors Nitayama, A, Aochi, H
Format Conference Proceeding
LanguageEnglish
Published IEEE 2010
Subjects
Conductivity
Costs
Delay estimation
FETs
Flash memory
Leakage current
Plugs
Stacking
Testing
Very large scale integration
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Summary:We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it to Pipe-shaped BiCS flash memory with U-shaped NAND string, improving the operation window and the reliability and realizing the Multi-Level-Cell (MLC) operation. The functionality has been successfully demonstrated using the 32 Gbit test chip with the 16 stacked layers and the MLC operation by 60nm P-BiCS flash technology.
ISBN:9781424450633
1424450632
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.2010.5488917