A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory

Most modern field-programmable gate arrays (FPGAs) employ a look-up table (LUT) as their basic logic cell. Although a k-input LUT can implement any k-input logic, its functionality relies on a large amount of configuration memory. As FPGA scales improve, the increased quantity of configuration memor...

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Published in2014 24th International Conference on Field Programmable Logic and Applications (FPL) pp. 1 - 6
Main Authors Qian Zhao, Yanagida, Kyosei, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
Format Conference Proceeding
LanguageEnglish
Published Technical University of Munich (TUM) 01.09.2014
Subjects
Benchmark testing
Delays
Field programmable gate arrays
Memory management
Microprocessors
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Summary:Most modern field-programmable gate arrays (FPGAs) employ a look-up table (LUT) as their basic logic cell. Although a k-input LUT can implement any k-input logic, its functionality relies on a large amount of configuration memory. As FPGA scales improve, the increased quantity of configuration memory cells required for FPGAs will require a larger area and consume more power. Moreover, the soft-error rate per device will also increase as more configuration memory cells are embedded. We propose scalable logic modules (SLMs), logic cells requiring less configuration memory, reducing configuration memory by making use of partial functions of Shannon expansion for frequently appearing logics. Experimental results show that SLM-based FPGAs use much less configuration memory and have smaller area than conventional LUT-based FPGAs.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2014.6927460