Acceleration of Functional Validation Using GPGPU

Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation...

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Bibliographic Details
Published in2011 Sixth IEEE International Symposium on Electronic Design, Test and Application pp. 211 - 216
Main Authors Suresh, L, Rameshan, N, Gaur, M S, Zwolinski, M, Laxmi, V
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2011
Subjects
Computational modeling
EDA
GPGPU
Graphics processing unit
Instruction sets
Integrated circuit modeling
Kernel
Logic gates
Logic Simulation
Pipeline processing
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Summary:Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation of combinational circuits on GPGPUs. Initial experiments run on two methods using benchmark circuits using NVIDIA GPGPUs suggest that these methods can be used for accelerating the EDA design flow process.
ISBN:9781424493579
1424493579
DOI:10.1109/DELTA.2011.46