FinFET: From compact modeling to circuit performance

FinFET device, the promise one of all candidates which may extend CMOS scaling to 10nm and beyond, has attracted intensive research interest in recent years. In paralleling the process technology and circuit design methodology, a compact model which serves as a link between the process technology an...

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Bibliographic Details
Published in2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 6
Main Authors He, F, Xingye Zhou, Chenyue Ma, Jian Zhang, Zhiwei Liu, Wen Wu, Xukai Zhang, Lining Zhang
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.12.2010
Subjects
circuit performance
CMOS integrated circuits
compact modeling
FinFET
Laboratories
Logic gates
reliability analysis
Semiconductor device modeling
simulation
Stress
Topology
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Summary:FinFET device, the promise one of all candidates which may extend CMOS scaling to 10nm and beyond, has attracted intensive research interest in recent years. In paralleling the process technology and circuit design methodology, a compact model which serves as a link between the process technology and circuit design is strongly demanded. In this paper, we first review the FinFET process technology including SOI-FinFET and bulk-FinFET. Then a potential-based compact model is proposed to describe the electrical characteristics of the FinFET transistor. The model is verified by 2-D numerical simulation and is implemented into HSPICE simulator. Finally, the reliability issue of the FinFET device and circuit functions are illustrated and analyzed, which are important for the practical applications and circuit design.
ISBN:9781424499977
1424499976
DOI:10.1109/EDSSC.2010.5713788