Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking

• Published in: 2010 IEEE International 3D Systems Integration Conference (3DIC) pp. 1 - 6
• Main Authors: Radu, I, Landru, D, Gaudin, G, Riou, G, Tempesta, C, Letertre, F, Di Cioccio, L, Gueguen, P, Signamarcheix, T, Euvrard, C, Dechamp, J, Clavelier, L, Sadaka, M
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.11.2010
• Subjects: 3D integration; Annealing; Bonding; bonding strength; Copper; Cu-Cu direct bonding; Electrical resistance measurement; electrical resistivity; Silicon; Surface topography; Surface treatment; wafer stacking; wafer-to-wafer alignment
• ISBN: 1457705265; 9781457705267
• DOI: 10.1109/3DIC.2010.5751454

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO 2 hybrid surfaces: copper dishing and erosion need to be minimized in order to obtain high bonding quality. The bonding quality is assessed by the evaluation of bonding strength, interfacial defects, wafer-to-wafer misalignment and electrical contact resistance at the Cu-Cu interface. The bonding strength evolution with post-bond annealing is reported and discussed for the case of patterned surfaces. Scanning Acoustic Microscopy (SAM) imaging of bonding interface is performed to monitor bonded defects. Process conditions have been optimized to minimize the post bond annealing (thermal budget) at temperatures below 400°C.