Word-parallel coprocessor architecture for digital nearest Euclidean distance search

• Published in: 2013 Proceedings of the ESSCIRC (ESSCIRC) pp. 267 - 270
• Main Authors: Akazawa, Toshinobu, Sasaki, Seiryu, Mattausch, Hans Jurgen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2013
• Subjects: Clocks; CMOS integrated circuits; Coprocessors; Data compression; Euclidean distance; Radiation detectors; Vectors
• ISBN: 9781479906437; 1479906433
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIRC.2013.6649124

The reported digital, word-parallel and scalable coprocessor architecture for nearest Euclidean distance (ED) search is based on mapping the distance into time domain onto an equivalent clock number. Area-efficient sequential square calculation and a minimization algorithm of the clock number necessary for the search are applied for practical efficiency. Experimental concept verification was done with an 180nm CMOS design implementing 32 reference vectors with 16 components and 8 bit per component. The fabricated test chips achieved 1.19μs average search time, 5.77 μs worst-case search time and low power dissipation of 8.75mW at 47MHz and Vdd=1.8V for code-book-based picture compression. To our best knowledge this is the first report of practical, word-parallel, digital nearest ED-search architecture. In comparison to previous digital-analog ASIC and GPU implementations, factors 1.8 and 4.5·10 5 smaller power delay products per 1NN search are realized, respectively.