Optimal Application Mapping on NoC Infrastructure using NSGA-II and MicroGA
Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In the platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) bl...
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Published in | 2009 International Conference on Intelligent Engineering Systems pp. 83 - 88 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English Japanese |
Published |
IEEE
01.04.2009
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Subjects | |
Online Access | Get full text |
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Summary: | Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In the platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this paper, we use multi-objective evolutionary optimization to address the problem of mapping topologically pre-selected sets IPs, which constitute the set of optimal solutions that were found for the IP assignment problem, on the tiles of a mesh-based NoC. The IP mapping optimization is driven by the area occupied, execution time and power consumption. |
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ISBN: | 9781424441112 1424441110 |
ISSN: | 1543-9259 |
DOI: | 10.1109/INES.2009.4924742 |