Advanced error prediction LDPC for high-speed reliable TLC nand-based SSDs

• Published in: 2014 IEEE 6th International Memory Workshop (IMW) pp. 1 - 4
• Main Authors: Tokutomi, Tsukasa, Tanakamaru, Shuhei, Iwasaki, Tomoko Ogura, Takeuchi, Ken
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2014
• Subjects: Bit error rate; Couplings; Error correcting code (ECC); Error correction codes; Flash memories; low density parity check code (LDPC); memory controller; Parity check codes; Reliability; solid state drive (SSD); triple level cell (TLC) NAND flash
• ISBN: 9781479935949; 1479935948
• ISSN: 2159-483X
• DOI: 10.1109/IMW.2014.6849375

Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flash's capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower V TH margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved reliability for Multi-Level-Cell (MLC) NAND flash [4]. However, in EP-LDPC program disturb is not modeled, so precision is limited, especially in short data retention <; 2 days. Here, AEP-LDPC is proposed for TLC NAND flash. By considering effects of program disturb, data retention and floating-gate capacitive coupling, the most accurate SSDs can be realized, with high speed read capability. The SSD's data-retention time increases by more than 12 x , decode iterations decrease 57% and acceptable TLC NAND BER increases by more than 2.8 ×.