Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectu...

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Bibliographic Details
Published in2003 Design, Automation and Test in Europe Conference and Exhibition pp. 296 - 301
Main Authors Bingfeng Mei, Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 2003
Subjects
Computer architecture
Field programmable gate arrays
Parallel processing
Processor scheduling
Reconfigurable architectures
Resource management
Routing
Scheduling algorithm
Testing
VLIW
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Summary:Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures. This algorithm is a key part of our dynamically reconfigurable embedded systems compiler (DRESC). It is capable of solving placement, scheduling and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture representation to model a wide class of coarse-grained architectures. The experimental results show high performance and efficient resource utilization on tested kernels.
ISBN:0769518702
9780769518701
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2003.1253623