Optimization and benchmarking of graphene-based heterostructure FETs

We compare the performance prospects of three recently proposed and demonstrated transistors based on vertical and lateral graphene-based heterostructures, with the requirements of the International Technology Roadmap for Semiconductors. All devices provide large Ion/Ioff ratios, but only the latera...

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Bibliographic Details
Published in2014 International Workshop on Computational Electronics (IWCE) pp. 1 - 3
Main Authors Logoteta, D., Fiori, G., Iannaccone, G.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.06.2014
Subjects
Delays
device simulation
Field effect transistors
Graphene
graphene transistors
heterostructures
Logic gates
Metals
nanoelectronics
Performance evaluation
TCAD
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Summary:We compare the performance prospects of three recently proposed and demonstrated transistors based on vertical and lateral graphene-based heterostructures, with the requirements of the International Technology Roadmap for Semiconductors. All devices provide large Ion/Ioff ratios, but only the lateral heterostructure field-effect transistors exhibit promising dynamic figures of merit, i.e. delay time and power-delay-product. The assessment is based on numerical simulations using our in-house nanoscale device simulation tool NanoTCAD Vides.
DOI:10.1109/IWCE.2014.6865838