Oblivious algorithms for multicores and network of processors

• Published in: 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS) pp. 1 - 12
• Main Authors: Chowdhury, Rezaul Alam, Silvestri, Francesco, Blakeley, Brandon, Ramachandran, Vijaya
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2010
• Subjects: algorithm; Algorithm design and analysis; cache; Computer networks; Design engineering; Gaussian elimination paradigm; list ranking; Microprocessors; multicore; Multicore processing; network; Network topology; oblivious; Parallel processing; Runtime; Scheduling algorithm; Sorting
• ISBN: 1424464420; 9781424464425
• ISSN: 1530-2075
• DOI: 10.1109/IPDPS.2010.5470354

We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hierarchical multi-level caching, and we introduce a multicore-oblivious (MO) approach to algorithms and schedulers for HM. An MO algorithm is specified with no mention of any machine parameters, such as the number of cores, number of cache levels, cache sizes and block lengths. However, it is equipped with a small set of instructions that can be used to provide hints to the run-time scheduler on how to schedule parallel tasks. We present efficient MO algorithms for several fundamental problems including matrix transposition, FFT, sorting, the Gaussian Elimination Paradigm, list ranking, and connected components. The notion of an MO algorithm is complementary to that of a network-oblivious (NO) algorithm, recently introduced by Bilardi et al. for parallel distributed-memory machines where processors communicate point-to-point. We show that several of our MO algorithms translate into efficient NO algorithms, adding to the body of known efficient NO algorithms.