Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data...

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Bibliographic Details
Published in2006 International Electron Devices Meeting pp. 1 - 4
Main Authors Shino, T., Kusunoki, N., Higashi, T., Ohsawa, T., Fujita, K., Hatsuda, K., Ikumi, N., Matsuoka, F., Kajitani, Y., Fukuda, R., Watanabe, Y., Minami, Y., Sakamoto, A., Nishimura, J., Nakajima, M., Morikado, M., Inoh, K., Hamamoto, T., Nitayama, A.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 2006
Subjects
Circuits
Data mining
Fabrication
Information systems
Large scale integration
Microelectronics
Random access memory
Read-write memory
Scalability
Threshold voltage
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Summary:Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
ISBN:142440438X
9781424404384
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346846