FD-SOI MOSFETs for the low-voltage nanoscale CMOS era

Limitations and challenges of FD-SOI MOSFETs are investigated in terms of intra- and inter-die V t -variations, and capabilities of the body-bias control and multi-V t MOSFETs. State-of-the-art planar FD-SOI MOSFETs are described, citing the SOTB (silicon on thin box) MOSFET as an example. FinFETs a...

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Bibliographic Details
Published in2009 IEEE International SOI Conference pp. 1 - 4
Main Authors Itoh, K., Sugii, N., Hisamoto, D., Tsuchiya, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2009
Subjects
CMOS technology
FinFETs
Laboratories
Logic circuits
Logic devices
MOSFETs
Nanoscale devices
Random access memory
Silicon
Voltage
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Summary:Limitations and challenges of FD-SOI MOSFETs are investigated in terms of intra- and inter-die V t -variations, and capabilities of the body-bias control and multi-V t MOSFETs. State-of-the-art planar FD-SOI MOSFETs are described, citing the SOTB (silicon on thin box) MOSFET as an example. FinFETs are also discussed; their challenges are clarified, and some solutions are proposed, such as high-density FinFETs and capacitors, and a small logic-process compatible DRAM cell. Finally, future prospects for the FD-SOI MOSFETs are presented.
ISBN:1424442567
9781424442560
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2009.5318750