Improved endurance of RRAM by optimizing reset bias scheme in 1T1R configuration to suppress reset breakdown

In this study, we reported suppressed reset breakdown, which causes endurance failure, by optimizing reset bias scheme in HfO 2 -based 1T1R RRAM device. Since the resistance of RRAM in reset operation controls effective transistor gate bias (V GS eff =V GS -I D *R RRAM ) which limits saturation drai...

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Bibliographic Details
Published in2016 IEEE Silicon Nanoelectronics Workshop (SNW) pp. 84 - 85
Main Authors Changhyuck Sung, Jeonghwan Song, Sangheon Lee, Hyunsang Hwang
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.06.2016
Subjects
Breakdown voltage
Electric breakdown
Hafnium oxide
Logic gates
Reliability
Resistors
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Summary:In this study, we reported suppressed reset breakdown, which causes endurance failure, by optimizing reset bias scheme in HfO 2 -based 1T1R RRAM device. Since the resistance of RRAM in reset operation controls effective transistor gate bias (V GS eff =V GS -I D *R RRAM ) which limits saturation drain current, optimum gate bias can supply sufficient reset current in low resistance state and limit current in high resistance state. As a result, the reset breakdown was successfully suppressed by applying optimum gate voltage and the endurance was significantly improved with maintaining high resistance ratio.
DOI:10.1109/SNW.2016.7577996