Fine grain incremental rescheduling via architectural retiming

• Published in: Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210) pp. 158 - 163
• Main Author: Hassoun, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: Clocks; Delay effects; Fabrication; High level synthesis; Integrated circuit interconnections; Logic gates; Pipeline processing; Size control; Very large scale integration; Wiring

With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact on delay and area. The need thus arises for developing techniques and tools to redesign incrementally to eliminate perform...