Fine grain incremental rescheduling via architectural retiming

• Published in: Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210) pp. 158 - 163
• Main Author: Hassoun, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: Clocks; Delay effects; Fabrication; High level synthesis; Integrated circuit interconnections; Logic gates; Pipeline processing; Size control; Very large scale integration; Wiring
• ISBN: 9780818686238; 0818686235
• ISSN: 1080-1820
• DOI: 10.1109/ISSS.1998.730619

With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact on delay and area. The need thus arises for developing techniques and tools to redesign incrementally to eliminate performance bottlenecks. Such a redesign effort corresponds to incrementally modifying an existing schedule obtained via high-level synthesis. In this paper we demonstrate that applying architectural retiming, a technique for pipelining latency-constrained circuits, results in incrementally modifying an existing schedule. Architectural retiming reschedules fine grain operations (ones that have a delay equal to or less than one clock cycle) to occur in earlier time steps, while modifying the design to preserve its correctness.