Techniques For The Trace-Driven Simulation Of Cache Performance

In contemporary computers, cache memories are interposed between processors and primary memories in order to decrease access time and bus traffic. Because the design of the cache is critical and the factors affecting its performance are complex, trace-driven simulation is widely used and studied. Th...

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Bibliographic Details
Published in1989 Winter Simulation Conference Proceedings pp. 1042 - 1046
Main Authors Eggers, S.J., Lazowska, E.D., Yi-Bing Lin
Format Conference Proceeding
LanguageEnglish
Published IEEE 1989
Subjects
Algorithm design and analysis
Analytical models
Cache memory
Compression algorithms
Computational modeling
Computer science
Design methodology
Performance analysis
Time measurement
Traffic control
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Summary:In contemporary computers, cache memories are interposed between processors and primary memories in order to decrease access time and bus traffic. Because the design of the cache is critical and the factors affecting its performance are complex, trace-driven simulation is widely used and studied. This paper surveys three interesting techniques for the trace-driven simulation of cache designs: stack analysis methodologies that make it possible to obtain performance measures for a wide variety of cache designs from a single run of the simulator, compression algorithms specifically tailored to memory reference traces, and an approach to parallel trace-driven simulation of multiprocessor caches that dramatically reduces the simulation's synchronization and thus its running time.
ISBN:0911801588
9780911801583
DOI:10.1109/WSC.1989.718790