System level synthesis for virtual memory enabled hardware threads

Newly introduced ARM-based FPGA platforms enable transparent hardware/software multithreading by providing cache-coherent memory accesses to hardware accelerators. However, the lack of support for virtual memory on the accelerator side hinders the use of off-the-shelf software stacks, such as offere...

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Bibliographic Details
Published in2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 738 - 743
Main Authors Estibals, Nicolas, Deest, Gael, El Moussawi, Ali Hassan, Derrien, Steven
Format Conference Proceeding Journal Article
LanguageEnglish
Published EDAA 01.03.2016
Subjects
Accelerators
Automation
Computer programs
Conferences
Exhibitions
Field programmable gate arrays
Hardware
Instruction sets
Memory management
Multithreading
Software
Virtual memory systems
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Summary:Newly introduced ARM-based FPGA platforms enable transparent hardware/software multithreading by providing cache-coherent memory accesses to hardware accelerators. However, the lack of support for virtual memory on the accelerator side hinders the use of off-the-shelf software stacks, such as offered by a Linux-based system, which limits their applicability in a legacy environment. To address this problem, we propose a fully automated high-level synthesis-based source-to-source flow to efficiently support virtual memory in hardware accelerators.
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ISSN:1558-1101