Modified CSD group multiplier design for predetermined coefficient groups

Some digital signal processing applications, such as FFT, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on a grouping method of CSD coefficients, an efficient multiplier design method for predetermined coefficient groups is proposed. In t...

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Bibliographic Details
Published in2008 IEEE International Symposium on Circuits and Systems pp. 3362 - 3365
Main Authors Kim, Yong-Eun, Cho, Su-Hyun, Chung, Jin-Gyun
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.01.2008
Subjects
Delay effects
Design methodology
Digital signal processing
Frequency synthesizers
Power generation
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Summary:Some digital signal processing applications, such as FFT, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on a grouping method of CSD coefficients, an efficient multiplier design method for predetermined coefficient groups is proposed. In the case of the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), it is shown that by the proposed method, area, power and delay time can be reduced by 53.1%, 45.6% and 22.6%, respectively, compared with conventional design. Also, in the case of multiplier design used in 128 point radix-2 4 FFT, the area, power and delay time can be reduced by 42.9%, 58.5% and 19.7%, respectively.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISBN:9781424416837
1424416833
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2008.4542179