Address assignment combined with scheduling in DSP code generation

One of the important issues in embedded system design is to optimize program code for the microprocessor to be stored in ROM. In this paper, we propose an integrated approach to the DSP address code generation problem for minimizing the number of addressing instructions. Unlike previous work in whic...

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Bibliographic Details
Published inProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) pp. 225 - 230
Main Authors Yoonseo Choi, Taewhan Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Computer science
Concurrent computing
Digital signal processing
Distributed power generation
Information technology
Permission
Processor scheduling
Registers
Semiconductor optical amplifiers
Signal processing algorithms
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Summary:One of the important issues in embedded system design is to optimize program code for the microprocessor to be stored in ROM. In this paper, we propose an integrated approach to the DSP address code generation problem for minimizing the number of addressing instructions. Unlike previous work in which code scheduling and offset assignment are performed sequentially without any interaction between them, our approach tightly couples the offset assignment problem with code scheduling to exploit scheduling on minimizing addressing instructions more effectively. We accomplish this by developing a fast but accurate two-phase procedure which, for a sequence of code schedules, finds a sequence of memory layouts with minimum addressing instructions. Experimental results with benchmark DSP programs show improvements of 13%-33% in the address code size over Solve-SOA/GOA.
ISBN:1581134614
9781581134612
ISSN:0738-100X
DOI:10.1109/DAC.2002.1012624