50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

• Published in: Digest. International Electron Devices Meeting pp. 69 - 72
• Main Authors: Kim, Y.W., Oh, C.B., Ko, Y.G., Lee, K.T., Ahn, J.H., Park, T.S., Kang, H.S., Lee, D.H., Jung, M.K., Yu, H.J., Jung, K.S., Liu, S.H., Oh, B.J., Kim, K.S., Lee, N.I., Park, M.H., Bae, G.J., Lee, S.G., Song, W.S., Wee, Y.G., Jeon, C.H., Suh, K.P.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Applied sciences; Circuit properties; CMOS logic circuits; CMOS technology; Compound structure devices; Dielectric devices; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; High K dielectric materials; High-K gate dielectrics; Integrated circuits; Integrated circuits by function (including memories and processors); Logic devices; Logic gates; MOS devices; Portfolios; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System-on-a-chip; Transistors; MIM structure; Dielectric materials; Random access memory; Transistor gate; Logic gate; Transistor; System on a chip; Logic circuit; Silicon on insulator technology; p channel; Microelectronic fabrication; SRAM chips; Interconnection; Gate oxide; Integrated circuit; Capacitance; Low-power electronics; NMOS technology; Capacitor; Chemical mechanical polishing
• ISBN: 9780780374621; 0780374622
• DOI: 10.1109/IEDM.2002.1175781

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.