Generalized sensitization using fault tuples

• Published in: 22nd IEEE VLSI Test Symposium, 2004. Proceedings pp. 297 - 303
• Main Authors: Biswas, S., Dwarakanath, K.N., Blanton, R.D.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004; IEEE Computer Society
• Subjects: Algebra; Analytical models; Applied sciences; Benchmark testing; Circuit analysis; Circuit faults; Circuit properties; Circuit simulation; Circuit testing; Delay effects; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Performance analysis; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing, measurement, noise and reliability; Theoretical study. Circuits analysis and design; Computation time; VLSI circuit; Integrated circuit testing; Network analysis; Integrated circuit; Testing equipment; Digital circuit; Delay time
• ISBN: 9780769521343; 0769521347
• ISSN: 1093-0167; 2375-1053
• DOI: 10.1109/VTEST.2004.1299256

Fault tuples have introduced a fault model independent methodology for digital circuit test analysis. However, the {0, 1, X} algebra currently used with fault tuples allows only one form of path sensitization. The sensitization options for fault tuples is enhanced based on a 5-value algebra. The 5-value algebra enables a more detailed test analysis through the selection of one of three types of sensitization. Simulation experiments performed using the ITC'99 benchmark circuits for transition and path delay faults reveal that faults can be simultaneously analyzed under different types of sensitization criteria with little increase in memory and CPU time.