A baseband processor for pulsed ultra-wideband signals
This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these sample...
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Published in | 2004 IEEE Custom Integrated Circuits Conference pp. 587 - 590 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
Piscataway NJ
IEEE
2004
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
ISBN | 0780384954 9780780384958 |
DOI | 10.1109/CICC.2004.1358892 |
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Summary: | This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 /spl mu/s. The baseband processor was implemented in the same 0.18 /spl mu/m CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated. |
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ISBN: | 0780384954 9780780384958 |
DOI: | 10.1109/CICC.2004.1358892 |