A baseband processor for pulsed ultra-wideband signals

This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these sample...

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Bibliographic Details
Published in2004 IEEE Custom Integrated Circuits Conference pp. 587 - 590
Main Authors Blazquez, R., Newaskar, P.P., Lee, F.S., Chandrakasan, A.P.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2004
Institute of Electrical and Electronics Engineers
Subjects
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ISBN0780384954
9780780384958
DOI10.1109/CICC.2004.1358892

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Summary:This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 /spl mu/s. The baseband processor was implemented in the same 0.18 /spl mu/m CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated.
ISBN:0780384954
9780780384958
DOI:10.1109/CICC.2004.1358892