A XiRisc-based SoC for embedded DSP applications

• Published in: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571) pp. 595 - 598
• Main Authors: Bocchi, M., De Bartolomeis, C., Mucci, C., Campi, F., Lodi, A., Toma, M., Canegallo, R., Guerrieri, R.
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2004; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; CMOS technology; Computer applications; Computer architecture; Design. Technologies. Operation analysis. Testing; Digital signal processing; Digital signal processing chips; Electronics; Embedded computing; Embedded system; Energy efficiency; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal processing; System-on-a-chip; Performance evaluation; System architecture; Prototype; Instruction sets; System design; System on a chip; Clock; Algorithm; Flexibility; Boarded computer; RISC processor; Embedded systems; Energetic efficiency; Complementary MOS technology; Integrated circuit; Signal processing; Reconfigurable architectures; Digital signal processor; Custom circuit
• ISBN: 0780384954; 9780780384958
• DOI: 10.1109/CICC.2004.1358894

Reconfigurable computing can face many of the current embedded systems design issues, providing a high degree of flexibility and increasing energy efficiency of computation. This paper introduces the architecture of a system on chip for signal processing applications, including an XiRisc reconfigurable processor as the main computational core. This RISC processor features an extensible instruction set, obtained through dynamic reconfiguration of a programmable gate-array embedded as a processor datapath function unit. A prototype chip has been implemented in 0.13 /spl mu/m CMOS technology. The SoC operates at 166 MHz clock speed and the test of several DSP algorithms showed speed-ups ranging from 5/spl times/ to 80/spl times/ with 65%-95% energy savings. As proof of the architectural improvement, energy and area computational efficiency has grown by a factor ranging from 3/spl times/ to 35/spl times/.